1. Technical Field of the Invention
The invention relates generally to communication systems; and, more particularly, it relates to decoding of LDPC (Low Density Parity Check) coded signals within such communication systems.
2. Description of Related Art
Data communication systems have been under continual development for many years. One such type of communication system that has been of significant interest lately is a communication system that employs iterative error correction codes. Of particular interest is a communication system that employs LDPC (Low Density Parity Check) code. Communications systems with iterative codes are often able to achieve lower bit error rates (BER) than alternative codes for a given signal to noise ratio (SNR).
A continual and primary directive in this area of development has been to try continually to lower the SNR required to achieve a given BER within a communication system. The ideal goal has been to try to reach Shannon's limit in a communication channel. Shannon's limit may be viewed as being the highest theoretically possible data rate to be used in a communication channel, having a particular SNR, that achieves error free transmission through the communication channel. In other words, the Shannon limit is the theoretical bound for channel capacity for a given modulation and code rate.
LDPC codes have been shown to provide for excellent decoding performance that can approach the Shannon limit in some cases. For example, some LDPC decoders have been shown to come within 0.3 dB (decibels) from the theoretical Shannon limit. While this example was achieved using an irregular LDPC code with a length of one million, it nevertheless demonstrates the very promising application of LDPC codes within communication systems.
The use of LDPC coded signals continues to be explored within many newer application areas. Some examples of possible communication systems that may employ LDPC coded signals include communication systems employing 4 wire twisted pair cables for high speed Ethernet applications (e.g., 10 Gbps (Giga-bits per second) Ethernet operation according to the IEEE 802.3an (10 GBASE-T) emerging standard) as well as communication systems operating within a wireless context (e.g., in the IEEE 802.11 context space including the IEEE 802.11n emerging standard).
For any of these particular communication system application areas, near-capacity achieving error correction codes are very desirable. The latency constraints, which would be involved by using traditional concatenated codes, simply preclude their use in such applications in very high data rate communication system application areas.
Generally speaking, within the context of communication systems that employ LDPC codes, there is a first communication device at one end of a communication channel with encoder capability and second communication device at the other end of the communication channel with decoder capability. In many instances, one or both of these two communication devices includes encoder and decoder capability (e.g., within a bi-directional communication system). LDPC codes can be applied in a variety of additional applications as well, including those that employ some form of data storage (e.g., hard disk drive (HDD) applications and other memory storage devices) in which data is encoded before writing to the storage media, and then the data is decoded after being read/retrieved from the storage media.
In many such prior art communication devices, one of the greatest hurdles and impediments in designing effective devices and/or communication devices that can decode LDPC coded signals is the typically large area and memory required to store and manage all of the updated bit edge messages and check edge messages that are updated and employed during iterative decoding processing (e.g., when storing and passing the check edges messages and the bit edges messages back and forth between a check engine and a bit engine, respectively). When dealing with relatively large block sizes in the context of LDPC codes, the memory requirements and memory management needed to deal with these check edges messages and bit edges messages can be very difficult to handle. There has been and continues to be a need in the art for better means by which LDPC coded signal can be decoded to extract the information encoded therein.
Moreover, when the size of a low density parity check matrix, H, employed to decode an LDPC coded signal reaches a certain size, the interconnectivity between a first processing module and a second processing module (e.g., a check engine and a bit engine) can significantly increase.